The present invention relates to a data demodulation system that can be used in magnetic recording, optical recording, etc.
One of the conventional sequential coding methods using constant ratio data codes of variable word length, for example, the 2-7 modulation/demodulation system is disclosed in the Japanese Unexamined Patent Publication Sho. 50-142131. In the 2-7 modulation/demodulation system, as shown in FIG. 2, 2-bit codes are used for 1-bit data, and when demodulating, in order to convert 2-bit codes into original 1-bit data, a demodulation clock DMCK is needed.
FIG. 3 refers to an example of a conventional demodulation circuit employed in the 2-7 modulation/demodulation system, in which the read data RDDT is introduced into a shift register 11 clocked by a read clock RDCK, and the output of the shift register 11 is introduced into a logic gate circuit 12. This output is synchronized by the 1/2 period read clock RDCK that has been introduced into a demodulation clock generator circuit 13, to produce a demodulated clock signal, clock DMCK, thereby obtaining demodulated data S20.
Thus, in the conventional circuit, since the modulation clock DMCK was obtained by compressing the read clock RDCK to 1/2 period by flip-flop 22 and AND gate 21, if wrong inversion occurred in the demodulation clock DMCK due to noise or other cause, all the subsequent demodulate data S20 would be wrong.